Semiconductor device and method for fabricating thereof

ABSTRACT

A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2022- 0009280 filed on Jan. 21, 2022, and No. 10-2022-0031447 filedon Mar. 14, 2022 in the Korean Intellectual Property Office, and all thebenefits accruing therefrom under 35 U.S.C. 119, the contents of whichin its entirety are herein incorporated by reference.

FIELD

The present disclosure relates to a semiconductor device and a methodfor fabricating the same, and more particularly, to a semiconductordevice including a multi-bridge channel field effect transistor(MBCFET™), and a method for fabricating the same.

BACKGROUND

As a scaling technology for increasing a density of a semiconductordevice, a multi-gate transistor has been proposed. In a multi-gatetransistor, a multi-channel active pattern (or a silicon body) having afin or nanowire shape may be formed on a substrate, and gates may beformed on a surface of the multi-channel active pattern.

Such a multi-gate transistor may have a three-dimensional channel, andit may thus be easier to perform scaling. In addition, a current controlcapability may be improved without increasing a gate length of themulti-gate transistor. Furthermore, a short channel effect (SCE) (inwhich a potential of a channel region is affected by a drain voltage)may be effectively suppressed.

SUMMARY

Aspects of the present disclosure provide a semiconductor device capableof improving performance and reliability of an element.

Aspects of the present disclosure also provide a method for fabricatinga semiconductor device capable of improving performance and reliabilityof an element.

However, aspects of the present disclosure are not restricted to thoseset forth herein. The above and other aspects of the present disclosurewill become more apparent to one of ordinary skill in the art to whichthe present disclosure pertains by referencing the detailed descriptionof the present disclosure given below.

According to an aspect of the present disclosure, a semiconductor devicecomprises an active pattern including a lower pattern extending in afirst direction and a plurality of sheet patterns spaced apart from thelower pattern in a second direction, a gate structure on the lowerpattern and including a gate insulating layer, a gate electrode, and agate spacer, the gate electrode extending in a third directionperpendicular to the first direction, a source/drain pattern on thelower pattern and in contact with the sheet patterns and the gateinsulating layer, and a first etch blocking pattern between the gatespacer and the source/drain pattern, wherein the gate spacer includes aninner sidewall facing the gate electrode and extending in the thirddirection, and a connection sidewall extending from the inner sidewallof the gate spacer in the first direction, the source/drain patternincludes a semiconductor liner layer and a semiconductor filling layeron the semiconductor liner layer, the semiconductor liner layer is incontact with the sheet pattern, and includes a facet surface extendingfrom the connection sidewall of the gate spacer, and the first etchblocking pattern is in contact with the facet surface of thesemiconductor liner layer and the connection sidewall of the gatespacer.

According to another aspect of the present disclosure, a semiconductordevice comprises an active pattern including a lower pattern extendingin a first direction and a plurality of sheet patterns spaced apart fromthe lower pattern in a second direction, a gate structure on the lowerpattern and including a gate insulating layer, a gate electrode, and agate spacer, the gate electrode extending in a third directionperpendicular to the first direction, and a source/drain pattern on thelower pattern and in contact with the sheet patterns and the gateinsulating layer, wherein the source/drain pattern includes asemiconductor liner layer and a semiconductor filling layer on thesemiconductor liner layer and in contact with the semiconductor linerlayer, the semiconductor liner layer is in contact with the sheetpatterns, and includes a facet surface extending from the gate spacer,and in plan view at a level of one of the sheet patterns, a first widthcomprising a maximum width of the semiconductor liner layer in the thirddirection is greater than a second width, in the third direction, of aninterface between the semiconductor liner layer and the semiconductorfilling layer.

According to still another aspect of the present disclosure, asemiconductor device comprises a first active pattern including a firstlower pattern extending in a first direction and a plurality of firstsheet patterns spaced apart from the first lower pattern in a seconddirection, a first gate structure on the first lower pattern andincluding a first gate insulating layer, a first gate electrode, and afirst gate spacer, the first gate electrode extending in a thirddirection perpendicular to the first direction, a second active patternincluding a second lower pattern extending in the first direction and aplurality of second sheet patterns spaced apart from the second lowerpattern in the second direction, a width of an upper surface of thesecond lower pattern in the third direction being smaller than a widthof an upper surface of the first lower pattern in the third direction, asecond gate structure on the second lower pattern and including a secondgate insulating layer, a second gate electrode, and a second gatespacer, the second gate electrode extending in the third direction, afirst source/drain pattern on the first lower pattern and in contactwith the first sheet patterns and the first gate insulating layer, asecond source/drain pattern on the second lower pattern and in contactwith the second sheet patterns and the second gate insulating layer, anda first etch blocking pattern between the first gate spacer and thefirst source/drain pattern, wherein the first gate spacer includes aninner sidewall facing the first gate electrode and extending in thethird direction and a connection sidewall extending from the innersidewall of the first gate spacer in the first direction, the firstsource/drain pattern includes a semiconductor liner layer and asemiconductor filling layer on the semiconductor liner layer, thesemiconductor liner layer is in contact with the first sheet pattern,and includes a facet surface extending from the connection sidewall ofthe first gate spacer, and the first etch blocking pattern is in contactwith the facet surface of the semiconductor liner layer and theconnection sidewall of the first gate spacer.

According to still another aspect of the present disclosure, a method offabricating a semiconductor device comprises forming a lower pattern andan upper pattern structure extending in a first direction, forming adummy gate structure on the upper pattern structure, the dummy gatestructure extending in a second direction and including a dummy gateelectrode and a pre-gate spacer on the dummy gate electrode, and thepre-gate spacer including an inner sidewall facing the dummy gateelectrode and extending in the second direction and a connectionsidewall extending from the inner sidewall of the pre-gate spacer in thefirst direction, forming a source/drain recess in the upper patternstructure using the dummy gate structure as a mask, the source/drainrecess exposing at least a portion of the connection sidewall of thepre-gate spacer, forming a semiconductor liner layer along a profile ofthe source/drain recess, the semiconductor liner layer including a facetsurface extending from the connection sidewall of the pre-gate spacer,forming an etch blocking pattern in contact with the facet surface ofthe semiconductor liner layer and the connection sidewall of thepre-gate spacer and extending in a third direction, and forming asemiconductor filling layer on the semiconductor liner layer after theforming of the etch blocking pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present disclosure willbecome more apparent by describing in detail example embodiments thereofwith reference to the attached drawings, in which:

FIG. 1 is an illustrative plan view for describing a semiconductordevice according to some embodiments;

FIGS. 2 and 3 are cross-sectional views taken along line A-A and lineB-B of FIG. 1 , respectively;

FIG. 4 is a view for describing a shape of a first sheet pattern of FIG.2 ;

FIG. 5 is a plan view taken along line C-C of FIG. 2 and viewed fromabove;

FIG. 6 is a plan view taken along line D-D of FIG. 2 and viewed fromabove;

FIG. 7 is an enlarged view of region P of FIG. 2 ;

FIG. 8 is an enlarged view of portion Q of FIG. 5 ;

FIGS. 9 and 10 are views for describing a semiconductor device accordingto some embodiments;

FIGS. 11 and 12 are views for describing a semiconductor deviceaccording to some embodiments;

FIGS. 13, 14, 15, and 16 are views for describing a semiconductor deviceaccording to some embodiments;

FIGS. 17, 18, and 19 are views for describing a semiconductor deviceaccording to some embodiments;

FIGS. 20 and 21 are views for describing a semiconductor deviceaccording to some embodiments;

FIGS. 22 and 23 are views for describing a semiconductor deviceaccording to some embodiments;

FIG. 24 is a view for describing a semiconductor device according tosome embodiments;

FIGS. 25, 26, and 27 are views for describing semiconductor devicesaccording to some embodiments, respectively;

FIGS. 28, 29, 30, and 31 are views for describing a semiconductor deviceaccording to some embodiments;

FIG. 32 is a view for describing a semiconductor device according tosome embodiments;

FIGS. 33, 34, and 35 are views for describing a semiconductor deviceaccording to some embodiments;

FIGS. 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,52, and 53 are views for describing intermediate steps of a method forfabricating a semiconductor device according to some embodiments;

FIGS. 54 and 55 are views for describing semiconductor devices accordingto some embodiments, respectively; and

FIGS. 56, 57, 58, and 59 are views for describing intermediate steps ofa method for fabricating a semiconductor device according to someembodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

A semiconductor device according to some embodiments may include atunneling field effect transistor (FET), a three-dimensional (3D) FET,or a two-dimensional material-based FET, and a heterostructure thereof.In addition, the semiconductor device according to some embodiments mayinclude a bipolar junction transistor, a lateral double-diffused metaloxide semiconductor (LDMOS) transistor, or the like.

A semiconductor device according to some embodiments will be describedwith reference to FIGS. 1 to 8 .

FIG. 1 is an illustrative plan view for describing a semiconductordevice according to some embodiments. FIGS. 2 and 3 are cross-sectionalviews taken along line A-A and line B-B of FIG. 1 , respectively. FIG. 4is a view for describing a shape of a first sheet pattern of FIG. 2 .FIG. 5 is a plan view taken along line C-C of FIG. 2 and viewed fromabove. FIG. 6 is a plan view taken along line D-D of FIG. 2 and viewedfrom above. FIG. 7 is an enlarged view of region P of FIG. 2 . FIG. 8 isan enlarged view of portion Q of FIG. 5 .

For reference, FIG. 1 schematically illustrates a semiconductor deviceexcept for a first gate insulating layer 130, an etch stop layer 185, aninterlayer insulating layer 190, a wiring structure 205, and the like.

Referring to FIGS. 1 to 8 , a semiconductor device according to someembodiments may include first active patterns AP1, a plurality of firstgate structures GS1, first source/drain patterns 150, and first sideetch blocking patterns 160. The terms “first,” “second,” “third,” etc.,may be used herein merely to distinguish one element from another.

A substrate 100 may be bulk silicon or silicon-on-insulator (SOI).Alternatively, the substrate 100 may be a silicon substrate or mayinclude other materials such as silicon germanium, silicon germanium oninsulator (SGOI), indium antimonide, a lead tellurium compound, indiumarsenide, indium phosphide, gallium arsenide, or gallium antimonide, butis not limited thereto.

The first active pattern AP1 may be disposed on the substrate 100. Thefirst active pattern AP1 may extend in a first direction D1. As anexample, the first active pattern AP1 may be disposed in a region wherea P-channel metal oxide semiconductor (PMOS) is formed. As anotherexample, the first active pattern AP1 may be disposed in a region wherean N-channel metal oxide semiconductor (NMOS) is formed. In thefollowing description, it will be described that the first activepattern AP1 is disposed in the region where the PMOS is formed.

The first active pattern AP1 may be a multi-channel active pattern. Thefirst active pattern AP1 may include a first lower pattern BP1 and aplurality of first sheet patterns NS1. The first lower pattern BP1 mayprotrude from the substrate 100. The first lower pattern BP1 may extendin the first direction D1.

The plurality of first sheet patterns NS1 may be disposed on an uppersurface BP1_US of the first lower pattern. The plurality of first sheetpatterns NS1 may be spaced apart from the first lower pattern BP1 in athird direction D3. The respective first sheet patterns NS1 may bespaced apart from each other in the third direction D3.

Each of the first sheet patterns NS1 may include an upper surface NS1_US and a lower surface NS1_BS. The upper surface NS1_US of the firstsheet pattern is a surface opposite to the lower surface NS1_BS of thefirst sheet pattern in the third direction D3. Each of the first sheetpatterns NS 1 may include first sidewalls NS1_SW1 opposite to each otherin the first direction D1 and second sidewalls NS1_SW2 opposite to eachother in a second direction D2. The third direction D3 may be adirection crossing the first direction D1 and a second direction D2. Forexample, the third direction D3 may be a thickness direction of thesubstrate 100. The first direction D1 may be a direction crossing thesecond direction D2.

The upper surface NS1_US of the first sheet pattern and the lowersurface NS1_BS of the first sheet pattern may be connected to each otherby the first sidewalls NS1_SW1 of the first sheet pattern and the secondsidewalls NS1_SW2 of the first sheet pattern. The first sidewall NS1_SW1of the first sheet pattern is connected to and in contact with a firstsource/drain pattern 150 to be described later. Elements described as“in contact with” may include direct contact therebetween. Elements aredescribed as in “direct” contact or “directly” on or connected have nointervening elements therebetween. The first sidewall NS1_SW1 of thefirst sheet pattern may include an end of the first sheet pattern NS1.For example, the end of the first sheet pattern NS1 may be positioned ata center line between the upper surface NS1_US of the first sheetpattern and the lower surface NS1_BS of the first sheet pattern, but isnot limited thereto.

It has been illustrated that three first sheet patterns NS1 are disposedin the third direction D3, but this is only for convenience ofexplanation, and the present disclosure is not limited thereto.

The first lower pattern BP1 may be formed by etching a portion of thesubstrate 100, and may include an epitaxial layer grown from thesubstrate 100. The first lower pattern BP1 may include silicon orgermanium, which is an elemental semiconductor material. In addition,the lower pattern BP1 may include a compound semiconductor, for example,a group IV-IV compound semiconductor or a group III-V compoundsemiconductor.

The group IV-IV compound semiconductor may be, for example, a binarycompound or a ternary compound including two or more of carbon (C),silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained bydoping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with agroup IV element.

The group III-V compound semiconductor may be, for example, one of abinary compound, a ternary compound, or a quaternary compound formed bycombining at least one of aluminum (Al), gallium (Ga), and indium (In),which are group III elements, with one of phosphorus (P), arsenic (As),and antimony (Sb), which are group V elements, with each other.

The first sheet pattern NS1 may include one of silicon or germanium,which is an elemental semiconductor material, a group IV-IV compoundsemiconductor, or a group III-V compound semiconductor. Each of thefirst sheet patterns NS 1 may include the same material as the firstlower pattern BP1 or include a material different from that of the firstlower pattern BP1.

In the semiconductor device according to some embodiments, the firstlower pattern BP1 may be a silicon lower pattern including silicon, andthe first sheet pattern NS1 may be a silicon sheet pattern includingsilicon.

Widths of the first sheet patterns NS1 in the second direction D2 mayincrease or decrease in proportion to a width of the first lower patternBP1 in the second direction D2. It has been illustrated by way ofexample that the widths, in the second direction, of the first sheetpatterns NS1 stacked in the third direction D3 are the same as eachother, but this is only for convenience of explanation, and the presentdisclosure is not limited thereto. Unlike illustrated in the drawings,the widths, in the second direction D2, of the first sheet patterns NS1stacked in the third direction D3 may decrease as the first sheetpatterns NS1 become distant from the first lower pattern BP1.

A field insulating layer 105 may be formed on the substrate 100. Thefield insulating layer 105 may be disposed on sidewalls of the firstlower pattern BP1. The field insulating layer 105 is not disposed on theupper surface BP1_US of the first lower pattern.

As an example, the field insulating layer 105 may entirely cover thesidewalls of the first lower pattern BP1. Unlike illustrated in thedrawings, the field insulating layer 105 may cover portions of thesidewalls of the first lower pattern BP1. In this case, portions of thefirst lower pattern BP1 may protrude more than an upper surface of thefield insulating layer 105 in the third direction D3.

Each of the first sheet patterns NS1 is disposed at a respective levelabove the upper surface of the field insulating layer 105. The fieldinsulating layer 105 may include, for example, an oxide layer, a nitridelayer, an oxynitride layer, or a combination thereof. It has beenillustrated that the field insulating layer 105 is a single layer, butthis is only for convenience of explanation, and the present disclosureis not limited thereto.

The plurality of first gate structures GS1 may be disposed on thesubstrate 100. Each of the first gate structures GS1 may extend in thesecond direction D2. The first gate structures GS1 may be disposed to bespaced apart from each other in the first direction D1 The first gatestructures GS1 may be adjacent to each other in the first direction D1For example, the first gate structures GS1 may be disposed on both sidesof the first source/drain pattern 150 in the first direction D1.

The first gate structure GS1 may be disposed on the first active patternAP1. The first gate structure GS1 may cross the first active patternAP1. The first gate structure GS1 may cross the first lower pattern BP1.The first gate structure GS1 may surround each of the first sheetpatterns NS1. The first gate structure GS1 may include, for example, afirst gate electrode 120, a first gate insulating layer 130, a firstgate spacer 140, and a first gate capping pattern 145.

The first gate structure GS1 may include a plurality of inner gatestructures INT1_GS1, INT2_GS1, and INT3_GS1 disposed between the firstsheet patterns NS1 adjacent to each other in the third direction D3 andbetween the first lower pattern BP 1 and the first sheet pattern NS1.The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 may bedisposed between the upper surface BP1_US of the first lower pattern andthe lower surface NS1_BS of the first lowermost sheet pattern andbetween the upper surface NS1_US of the first sheet pattern and thelower surface NS1_BS of the first sheet pattern facing each other in thethird direction D3. For example, the number of inner gate structuresINT1_GS1, INT2_GS1, and INT3_GS1 may be the same as the number of firstsheet patterns NS1.

The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 are incontact with the upper surface BP1_US of the first lower pattern, theupper surface NS1_US of the first sheet pattern, and the lower surfaceNS1_BS of the first sheet pattern. The inner gate structures INT1_GS1,INT2_GS1, and INT3_GS1 may be in direct contact with a firstsource/drain pattern 150 to be described later.

The first gate structure GS1 may include a first inner gate structureINT1_GS1, a second inner gate structure INT2_GS1, and a third inner gatestructure INT3_GS1. The first inner gate structure INT1_GS1, the secondinner gate structure INT2_GS1, and the third inner gate structureINT3_GS1 may be sequentially disposed on the first lower pattern BP1.

The third inner gate structure INT3_GS1 may be disposed between thefirst lower pattern BP1 and the first sheet pattern NS1. The third innergate structure INT3_GS1 may be disposed at the lowermost portion amongthe inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1. The thirdinner gate structure INT3_GS1 may be the lowermost inner gate structure.

The first inner gate structure INT1_GS1 and the second inner gatestructure INT2_GS1 may be disposed between the first sheet patterns NS1adjacent to each other in the third direction D3. The first inner gatestructure INT1_GS1 may be disposed at the uppermost portion among theinner gate structures INT1_GS1, INT2_GS1, and INT3_GS1. The first innergate structure INT1_GS1 may be the uppermost inner gate structure. Thesecond inner gate structure INT2_GS1 is disposed between the first innergate structure INT1_GS1 and the third inner gate structure INT3_GS1.

The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 include firstgate electrodes 120 and first gate insulating layers 130 disposedbetween the first sheet patterns NS1 adjacent to each other and betweenthe first lower pattern BP1 and the first sheet pattern NS1.

As an example, a width of the first inner gate structure INT1_GS1 in thefirst direction D1 may be the same as a width of the second inner gatestructure INT2_GS1 in the first direction D1. A width of the third innergate structure INT3_GS1 in the first direction D1 may be the same as awidth of the second inner gate structure INT2_GS1 in the first directionD1.

As another example, a width of the third inner gate structure INT3_GS1in the first direction D1 may be greater than a width of the secondinner gate structure INT2_GS1 in the first direction D1. A width of thefirst inner gate structure INT1_GS1 in the first direction D1 may be thesame as a width of the second inner gate structure INT2_GS1 in the firstdirection D1.

Taking the second inner gate structure INT2_GS1 as an example, the widthof the second inner gate structure INT2_GS1 may be measured in themiddle between the upper surface NS1_US of the first sheet pattern andthe lower surface NS1_BS of the first sheet pattern facing each other inthe third direction D3.

For reference, a plan view at a level (i.e., a height relative to thesubstrate 100 or other reference feature) of the second inner gatestructure INT2_GS1 is illustrated in FIG. 5 . A plan view at a level ofthe first lowermost sheet pattern NS1 most adjacent to the first lowerpattern BP1 among the first sheet patterns NS1 is illustrated in FIG. 6. Although not illustrated in the drawings, when a portion where a firstsource/drain contact 180 is formed is excluded, plan views at levels ofthe other inner gate structures INT1_GS1 and INT3_GS1 may be similar toFIG. 5 . Although not illustrated in the drawings, when the portionwhere the first source/drain contact 180 is formed is excluded, planviews at levels of the other first sheet patterns NS1 may be similar toFIG. 6 .

The first gate electrode 120 may be disposed on the first lower patternBP1. The first gate electrode 120 may cross the first lower pattern BP1.The first gate electrode 120 may surround the first sheet patterns NS1.Portions of the first gate electrode 120 may be disposed between thefirst sheet patterns NS1 adjacent to each other and between the firstlower pattern BP1 and the first sheet pattern NS1.

The first gate electrode 120 may include at least one of a metal, ametal alloy, conductive metal nitride, metal silicide, a dopedsemiconductor material, conductive metal oxide, and conductive metaloxynitride. The first gate electrode 120 may include, for example, atleast one of titanium nitride (TiN), tantalum carbide (TaC), tantalumnitride (TaN), titanium silicon nitride (TiSiN), tantalum siliconnitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminumnitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride(WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminumcarbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titaniumcarbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum(Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel(Ni), platinum (Pt)), nickel platinum (Ni-Pt), niobium (Nb), niobiumnitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenumnitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium(Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au),zinc (Zn), vanadium (V), and combinations thereof, but is not limitedthereto. The conductive metal oxide and the conductive metal oxynitridemay include oxidized forms of the above-described materials, but are notlimited thereto.

The first gate electrodes 120 may be disposed on both sides of a firstsource/drain pattern 150 to be described later. The first gatestructures GS1 may be disposed on both sides of the first source/drainpattern 150 in the first direction D1.

As an example, both of the first gate electrodes 120 disposed on bothsides of the first source/drain pattern 150 may be normal gateelectrodes used as gates of transistors. As another example, the firstgate electrode 120 disposed on one side of the first source/drainpattern 150 may be used as a gate of a transistor, but the first gateelectrode 120 disposed on the other side of the first source/drainpattern 150 may be a dummy gate electrode.

The first gate insulating layer 130 may extend along the upper surfaceof the field insulating layer 105 and the upper surface BP1_US of thefirst lower pattern. The first gate insulating layer 130 may surroundthe plurality of first sheet patterns NS1. The first gate insulatinglayer 130 may be disposed along circumferences of the first sheetpatterns NS1. The first gate electrode 120 is disposed on the first gateinsulating layer 130. The first gate insulating layer 130 is disposedbetween the first gate electrode 120 and the first sheet patterns NS1.Portions of the first gate insulating layer 130 may be disposed betweenthe first sheet patterns NS1 adj acent to each other in the thirddirection D3 and between the first lower pattern BP1 and the first sheetpattern NS1.

The first gate insulating layer 130 may include silicon oxide,silicon-germanium oxide, germanium oxide, silicon oxynitride, siliconnitride, or a high-k material having a dielectric constant greater thanthat of the silicon oxide. The high-k material may include, for example,one or more of boron nitride, hafnium oxide, hafnium silicon oxide,hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, or lead zinc niobate.

It has been illustrated that the first gate insulating layer 130 is asingle layer, but this is only for convenience of explanation, and thepresent disclosure is not limited thereto. The first gate insulatinglayer 130 may include a plurality of layers. The first gate insulatinglayer 130 may include an interfacial layer disposed between the firstsheet pattern NS1 and the first gate electrode 120 and a high-kinsulating layer.

The semiconductor device according to some embodiments may include anegative capacitance (NC) FET using a negative capacitor. For example,the first gate insulating layer 130 may include a ferroelectric materiallayer having ferroelectric characteristics and a paraelectric materiallayer having paraelectric characteristics.

The ferroelectric material layer may have a negative capacitance, andthe paraelectric material layer may have a positive capacitance. Forexample, when two or more capacitors are connected to each other inseries and capacitances of respective capacitors have a positive value,a total capacitance decreases as compared with a capacitance of eachindividual capacitor. On the other hand, when at least one ofcapacitances of two or more capacitors connected to each other in serieshas a negative value, a total capacitance may have a positive value andbe greater than an absolute value of each individual capacitance.

When the ferroelectric material layer having negative capacitance andthe paraelectric material layer having positive capacitance areconnected to each other in series, the total capacitance value of theferroelectric material layer and the paraelectric material layerconnected to each other in series may increase. A transistor includingthe ferroelectric material layer may have a subthreshold swing (SS) lessthan 60 mV/decade at room temperature using the increase in the totalcapacitance value.

The ferroelectric material layer may have ferroelectric characteristics.The ferroelectric material layer may include, for example, at least oneof hafnium oxide, hafnium zirconium oxide, barium strontium titaniumoxide, barium titanium oxide, and lead zirconium titanium oxide. Here,as an example, the hafnium zirconium oxide may be a material obtained bydoping hafnium oxide with zirconium (Zr). As another example, thehafnium zirconium oxide may be a compound of hafnium (Hf), zirconium(Zr), and oxygen (O).

The ferroelectric material layer may further include a dopant. Forexample, the dopant may include at least one of aluminum (Al), titanium(Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon(Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er),gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin(Sn). A type of dopant included in the ferroelectric material layer maychange depending on a type of ferroelectric material included in theferroelectric material layer.

When the ferroelectric material layer includes hafnium oxide, the dopantincluded in the ferroelectric material layer may include, for example,at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum(Al), and yttrium (Y).

When the dopant is aluminum (Al), the ferroelectric material layer mayinclude 3 to 8 atomic % (at%) of aluminum. Here, a ratio of the dopantmay be a ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material layer mayinclude 2 to 10 at% of silicon. When the dopant is yttrium (Y), theferroelectric material layer may include 2 to 10 at% of yttrium. Whenthe dopant is gadolinium (Gd), the ferroelectric material layer mayinclude 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), theferroelectric material layer may include 50 to 80 at% of zirconium.

The paraelectric material layer may have the paraelectriccharacteristics. The paraelectric material layer may include, forexample, at least one of silicon oxide and metal oxide having a highdielectric constant. The metal oxide included in the paraelectricmaterial layer may include, for example, at least one of hafnium oxide,zirconium oxide, and aluminum oxide, but is not limited thereto.

The ferroelectric material layer and the paraelectric material layer mayinclude the same material. The ferroelectric material layer may haveferroelectric characteristics, but the paraelectric material layer maynot have ferroelectric characteristics. For example, when theferroelectric material layer and the paraelectric material layer includehafnium oxide, a crystal structure of the hafnium oxide included in theferroelectric material layer is different from a crystal structure ofthe hafnium oxide included in the paraelectric material layer.

The ferroelectric material layer may have a thickness havingferroelectric characteristics. The thickness of the ferroelectricmaterial layer may be, for example, 0.5 to 10 nm, but is not limitedthereto. Since a critical thickness to produce ferroelectriccharacteristics may be different for each ferroelectric material, thethickness of the ferroelectric material layer may change depending onthe ferroelectric material.

As an example, the first gate insulating layer 130 may include oneferroelectric material layer. As another example, the first gateinsulating layer 130 may include a plurality of ferroelectric materiallayers spaced apart from each other. The first gate insulating layer 130may have a stacked layer structure in which a plurality of ferroelectricmaterial layers and a plurality of paraelectric material layers arealternately stacked.

The first gate spacer 140 may be disposed on a sidewall of the firstgate electrode 120. The first gate spacer 140 may not be disposedbetween the first lower pattern BP1 and the first sheet pattern NS1 andbetween the first sheet patterns NS1 adjacent to each other in the thirddirection D3.

The first gate spacer 140 may include an inner sidewall 140_ISW, aconnection sidewall 140_CSW, and an outer sidewall 140_OSW. The innersidewall 140_ISW of the first gate spacer faces the sidewall of thefirst gate electrode 120 extending in the second direction D2. The innersidewall 140_ISW of the first gate spacer may extend in the seconddirection D2. The inner sidewall 140_ISW of the first gate spacer may bea surface opposite the outer sidewall 140_OSW of the first gate spacerfacing a first interlayer insulating layer 190. The connection sidewall140_CSW of the first gate spacer connects the inner sidewall 140_ISW2 ofthe first gate spacer and the outer sidewall 140_OSW of the first gatespacer to each other. The connection sidewall 140_CSW of the first gatespacer may extend in the first direction D1.

The first gate insulating layer 130 may extend along the inner sidewall140_ISW of the first gate spacer. The first gate insulating layer 130may be in contact with the inner sidewall 140_ISW of the first gatespacer.

The first gate spacer 140 may include, for example, at least one ofsilicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO₂),silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), siliconoxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinationsthereof. It has been illustrated that the first gate spacer 140 is asingle layer, but this is only for convenience of explanation, and thepresent disclosure is not limited thereto.

The first gate capping pattern 145 may be disposed on the first gateelectrode 120 and the first gate spacer 140. An upper surface of thefirst gate capping pattern 145 may be coplanar with an upper surface ofthe interlayer insulating layer 190. Unlike illustrated in the drawings,the first gate capping pattern 145 may be disposed between the firstgate spacers 140.

The first gate capping pattern 145 may include, for example, at leastone of silicon nitride (SiN), silicon oxynitride (SiON), siliconcarbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinationsthereof. The first gate capping pattern 145 may include a materialhaving an etch selectivity with respect to the interlayer insulatinglayer 190.

The first source/drain pattern 150 may be disposed on the first activepattern AP1. The first source/drain pattern 150 may be disposed on thefirst lower pattern BP1. The first source/drain pattern 150 is connectedto the first sheet patterns NS1.

The first source/drain pattern 150 may be disposed on a side of thefirst gate structure GS1. The first source/drain pattern 150 may bedisposed between the first gate structures GS1 adjacent to each other inthe first direction D1. For example, the first source/drain patterns 150may be disposed on both sides of the first gate structure GS1. Incontrast to the illustration in the drawings, the first source/drainpattern 150 may be disposed on one side of the first gate structure GS1and may not be disposed on the other side of the first gate structureGS1.

The first source/drain pattern 150 may be included in a source/drain ofa transistor using the first sheet pattern NS1 as a channel region.

The first source/drain pattern 150 may be disposed in a firstsource/drain recess 150R. The first source/drain recess 150R extends inthe third direction D3. The first source/drain recess 150R may bedefined between the first gate structures GS1 adjacent to each other inthe first direction D1.

A bottom surface of the first source/drain recess 150R is defined by thefirst lower pattern BP1. Sidewalls of the first source/drain recess 150Rmay be defined by the first sheet patterns NS1 and the inner gatestructures INT1_GS1, INT2_GS1, and INT3_GS1 The inner gate structuresINT1_GS1, INT2_GS1, and INT3_GS1 may define portions of the sidewalls ofthe first source/drain recess 150R. In FIGS. 5 and 6 , the firstsource/drain recess 150R includes the connection sidewall 140_CSW of thefirst gate spacer.

The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 may includeupper surfaces facing the lower surfaces NS1_BS of the first sheetpatterns. The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1include lower surfaces facing the upper surfaces NS1_US of the firstsheet patterns or the upper surface BP1_US of the first lower pattern.The inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 includesidewalls connecting the upper surfaces of the inner gate structuresINT1_GS1, INT2_GS1, and INT3_GS1 and the lower surfaces of the innergate structures INT1_GS1, INT2_GS1, and INT3_GS1 to each other. Thesidewalls of the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1may define portions of the sidewalls of the first source/drain recess150R.

Between the first sheet pattern NS1 disposed at the lowermost portionand the first lower pattern BP1, a boundary between the first gateinsulating layer 130 and the first lower pattern BP1 may be the uppersurface BP1_US of the first lower pattern. The upper surface BP1_US ofthe first lower pattern may be a boundary between the third inner gatestructure INT3_GS1 and the first lower pattern BP1.

Width extension regions 150R_ER of the first source/drain recess may bedefined between the first sheet patterns NS1 adjacent to each other inthe third direction D3. The width extension region 150R_ER of the firstsource/drain recess may be defined between the first lower pattern BP1and the first sheet pattern NS1. The width extension regions 150R_ER ofthe first source/drain recess may extend between the first sheetpatterns NS1 adjacent to each other in the third direction D3. The widthextension regions 150R_ER of the first source/drain recess may bedefined between the inner gate structures INT1_GS1, INT2_GS1, andINT3_GS1 adjacent to each other in the first direction D1.

The width extension region 150R_ER of each of the first source/drainrecesses may include a portion where a width thereof in the firstdirection D1 increases and a portion where a width thereof in the firstdirection D1 decreases as it moves away from the upper surface BP1_US ofthe first lower pattern. For example, the width of the width extensionregion 150R_ER of the first source/drain recess may increase and thendecrease in the direction away from the upper surface BP1_US of thefirst lower pattern.

In the width extension region 150R_ER of each of the first source/drainrecesses, a point where the width extension region 150R_ER of the firstsource/drain recess has a maximum width is positioned between the firstsheet pattern NS1 and the first lower pattern BP1 or between the firstsheet patterns NS1 adjacent to each other in the third direction D3.

The first source/drain pattern 150 may be in contact with the firstsheet pattern NS1 and the first lower pattern BP1. A portion of thefirst source/drain pattern 150 may be in contact with the connectionsidewall 140_CSW of the first gate spacer. The first gate insulatinglayers 130 of the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1may be in contact with the first source/drain pattern 150.

The first source/drain pattern 150 may include an epitaxial pattern. Thefirst source/drain pattern 150 includes a semiconductor material. Thefirst source/drain pattern 150 may include a first semiconductor linerlayer 151 and a first semiconductor filling layer 152. It has beenillustrated that the first semiconductor filling layer 152 is a singlelayer, but this is only for convenience of explanation, and the presentdisclosure is not limited thereto.

The first semiconductor liner layer 151 may be continuously formed alongthe first source/drain recess 150R. The first semiconductor liner layer151 may be formed along the sidewalls of the first source/drain recess150R and the bottom surface of the first source/drain recess 150R. Thefirst semiconductor liner layer 151 formed along the first source/drainrecess 150R defined by the first sheet patterns NS1 is directlyconnected to the first semiconductor liner layer 151 formed along thefirst source/drain recess 150R defined by the inner gate structuresINT1_GS1, INT2_GS1, and INT3_GS1. The first semiconductor liner layer151 is in contact with the first gate insulating layers 130, the firstsheet patterns NS1, and the first lower pattern BP1.

The first semiconductor liner layer 151 may include an outer sidewall151_OSW and an inner sidewall 151_ISW. The outer sidewall 151_OSW of thefirst semiconductor liner layer 151 is in contact with the first gateinsulating layers 130, the first sheet patterns NS1, and the first lowerpattern BP1. The outer sidewall 151_OSW of the first semiconductor linerlayer is directly connected to the first sidewalls NS1_SW1 of the firstsheet patterns. The outer sidewall 151_OSW of the first semiconductorliner layer is in contact with the sidewalls of the inner gatestructures INT1_GS1, INT2_GS1, and INT3_GS1. The outer sidewall 151_OSWof the first semiconductor liner layer may represent a profile of thefirst source/drain recess 150R.

The inner sidewall 151_ISW of the first semiconductor liner layer may bea surface opposite to the outer sidewall 151_OSW of the firstsemiconductor liner layer. In FIGS. 5 and 6 , the first semiconductorliner layer 151 may include a portion where a width thereof in thesecond direction D2 decreases in the direction away from the outersidewall 151_OSW of the first semiconductor liner layer 151. The innersidewall 151_ISW of the first semiconductor liner layer may include afacet surface 151_FSW and a connection surface 151_CSW.

The facet surface 151_FSW of the inner sidewall 151_ISW of the firstsemiconductor liner layer may extend from the connection sidewall140_CSW of the first gate spacer. The facet surface 151_FSW of the innersidewall 151_ISW of the first semiconductor liner layer may form anacute angle with the connection sidewall 140_CSW of the first gatespacer. The first semiconductor liner layer 151 includes the facetsurface 151_FSW extending from the connection sidewall 140_CSW of thefirst gate spacer. The facet surface 151_FSW of the inner sidewall151_ISW of the first semiconductor liner layer may be a facet surface ofthe first semiconductor liner layer 151.

The connection surface 151_CSW of the inner sidewall 151_ISW of thefirst semiconductor liner layer may extend in the second direction D2.The connection surface 151_CSW of the inner sidewall 151_ISW of thefirst semiconductor liner layer may include a curved portion.

It has been illustrated in FIGS. 2, 5 and 6 that a thickness, in thefirst direction D1, of the first semiconductor liner layer 151 incontact with the first sidewalls NS1_SW1 of the first sheet patterns issmaller than a thickness, in the first direction D1, of the firstsemiconductor liner layer 151 in contact with the inner gate structuresINT1_GS1, INT2_GS1, and INT3_GS1, but the present disclosure is notlimited thereto.

The first semiconductor liner layer 151 may include, for example,silicon-germanium. The first semiconductor liner layer 151 may include asilicon-germanium layer. The first semiconductor liner layer 151 mayinclude doped p-type impurities. For example, the p-type impurities maybe boron (B), but are not limited thereto.

The first semiconductor filling layer 152 is disposed on the firstsemiconductor liner layer 151. The first semiconductor filling layer 152is in contact with the first semiconductor liner layer 151. In FIG. 2 ,the first semiconductor filling layer 152 may fill the remainder of thefirst source/drain recess 150R.

The first semiconductor filling layer 152 is disposed on the innersidewall 151_ISW of the first semiconductor liner layer. For example,the first semiconductor filling layer 152 may be in contact with theinner sidewall 151_ISW of the first semiconductor liner layer.

The first semiconductor filling layer 152 may cover a portion of theinner sidewall 151_ISW of the first semiconductor liner layer. In FIGS.5 and 6 , the first semiconductor filling layer 152 may not cover atleast a portion of the facet surface 151_FSW of the inner sidewall151_ISW of the first semiconductor liner layer. The first semiconductorfilling layer 152 may cover at least a portion of the connection surface151_CSW of the inner sidewall 151_ISW of the first semiconductor linerlayer.

The first semiconductor filling layer 152 may include, for example,silicon-germanium. The first semiconductor filling layer 152 may includea silicon-germanium layer. The first semiconductor filling layer 152 mayinclude doped p-type impurities. A fraction of germanium in the firstsemiconductor liner layer 151 is smaller than a fraction of germanium inthe first semiconductor filling layer 152.

Although not illustrated in the drawings, as an example, a semiconductorcapping layer including silicon may be disposed on the firstsemiconductor filling layer 152. As another example, a semiconductorcapping layer including silicon germanium may be disposed on the firstsemiconductor filling layer 152. In this case, a fraction of germaniumin the semiconductor capping layer may be smaller than a fraction ofgermanium in the first semiconductor filling layer 152.

The first side etch blocking pattern 160 is disposed between the firstgate spacer 140 and the first source/drain pattern 150. The first sideetch blocking pattern 160 may be disposed between the first gate spacer140 and the first semiconductor liner layer 151.

In FIGS. 5 and 6 , the first side etch blocking pattern 160 may extendalong the third direction D3 between the first gate spacer 140 and thefirst source/drain pattern 150.

In FIGS. 2 and 5 , the first side etch blocking pattern 160 is disposedbetween the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 andthe first semiconductor filling layer 152.

The first side etch blocking pattern 160 is disposed between theconnection sidewall 140_CSW of the first gate spacer and the facetsurface 151_FSW of the inner sidewall 151_ISW of the first semiconductorliner layer. That is, the first side etch blocking pattern 160 isdisposed between the connection sidewall 140_CSW of the first gatespacer and the facet surface of the first semiconductor liner layer 151.

The first side etch blocking pattern 160 is in contact with the firstgate spacer 140 and the first source/drain pattern 150. For example, thefirst side etch blocking pattern 160 is in direct contact with the firstgate spacer 140 and the first source/drain pattern 150. The first sideetch blocking pattern 160 is in contact with the connection sidewall140_CSW of the first gate spacer and the facet surface 151_FSW of theinner sidewall 151_ISW of the first semiconductor liner layer.

A width of the first side etch blocking pattern 160 in the seconddirection D2 may increase in the direction away from the first gateelectrode 120. In the plan view, the first side etch blocking pattern160 may have a substantially triangular shape.

The first side etch blocking pattern 160 may include at least onesubstantially linear surface (referred to herein with reference to afirst inclined surface 160_SS1, and a second inclined surface 160_SS2),and a (non-linear) connection surface 160_CS. The first inclined surface160_SS1 of the first side etch blocking pattern faces the connectionsidewall 140_CSW of the first gate spacer. The first inclined surface160_SS1 of the first side etch blocking pattern is in contact with theconnection sidewall 140_CSW of the first gate spacer. The secondinclined surface 160_SS2 of the first side etch blocking pattern facesthe facet surface of the first semiconductor liner layer 151. The secondinclined surface 160_SS2 of the first side etch blocking pattern is incontact with the facet surface of the first semiconductor liner layer151.

The connection surface 160_CS of the first side etch blocking patternconnects the first inclined surface 160_SS1 of the first side etchblocking pattern and the second inclined surface 160_SS2 of the firstside etch blocking pattern to each other. According to some embodiments,the entirety of the connection surface 160_CS of the first side etchblocking pattern may be in contact with the first source/drain pattern150. For example, the entirety of the connection surface 160_CS of thefirst side etch blocking pattern may be in contact with the firstsemiconductor filling layer 152.

In FIG. 5 , the first side etch blocking pattern 160 may protrude towardthe first gate electrode 120 less than the outer sidewall 151_OSW of thefirst semiconductor liner layer. In FIG. 6 , the first side etchblocking pattern 160 protrudes toward the first sheet pattern NS1 lessthan the outer sidewall 151_OSW of the first semiconductor liner layer.

In the plan view, the first side etch blocking pattern 160 covers atleast a portion of the facet surface of the first semiconductor linerlayer 151. The first semiconductor filling layer 152 may be in contactwith a portion of the facet surface of the first semiconductor linerlayer 151. In contrast to the illustration in the drawings, when thefirst side etch blocking pattern 160 covers the entirety of the facetsurface of the first semiconductor liner layer 151, the firstsemiconductor filling layer 152 is not contact with the facet surface ofthe first semiconductor liner layer 151.

In FIG. 5 , a maximum width of the first semiconductor liner layer 151in the second direction D2 is a first width W11. A width, in the seconddirection D2, of an interface between the first semiconductor linerlayer 151 and the first semiconductor filling layer 152 is a secondwidth W21. Since the first side etch blocking pattern 160 covers aportion of the inner sidewall 151_ISW of the first semiconductor linerlayer, the first width W11 is greater than the second width W21. Here,the interface between the first semiconductor liner layer 151 and thefirst semiconductor filling layer 152 is a contact surface between thefirst semiconductor liner layer 151 and the first semiconductor fillinglayer 152.

In FIG. 6 , a maximum width of the first semiconductor liner layer 151in the second direction D2 is a third width W12. A width, in the seconddirection D2, of the interface between the first semiconductor linerlayer 151 and the first semiconductor filling layer 152 is a fourthwidth W22. The third width W12 is greater than the fourth width W22.

In FIG. 5 , a thickness or dimension of the first side etch blockingpattern 160 in the first direction D1 is a first thickness T11. In FIG.6 , a thickness or dimension of the first side etch blocking pattern 160in the first direction D1 is a second thickness T12. It has beenillustrated in FIGS. 5 and 6 that the thickness T11 of the first sideetch blocking pattern 160 at a level of the inner gate structure isgreater than the thickness T12 of the first side etch blocking pattern160 at a level of the first sheet pattern, but this is only forconvenience of explanation, and the present disclosure is not limitedthereto.

As an example, the first side etch blocking pattern 160 may include aninsulating material. For example, the first side etch blocking pattern160 may include at least one of silicon nitride and silicon carbide, butis not limited thereto. As another example, the first side etch blockingpattern 160 may include a semiconductor material. For example, the firstside etch blocking pattern 160 may include silicon, but is not limitedthereto. As another example, the first side etch blocking pattern 160may include a metal.

In the following description, the first side etch blocking pattern 160includes an insulating material. For example, the first side etchblocking pattern 160 may include silicon nitride.

In FIGS. 48 and 53 , while a sacrificial pattern SC_L is removed, anetchant for removing the sacrificial pattern SC_L may permeate throughthe vicinity of the connection sidewall 140_CSW of the first gatespacer. The permeating etchant etches the first semiconductor fillinglayer 152, and thus, reliability and performance of the semiconductordevice may be deteriorated.

However, the first side etch blocking pattern 160 is formed between thefirst gate spacer 140 and the first semiconductor liner layer 151, andthus, the permeation of the etchant through the vicinity of theconnection sidewall 140_CSW of the first gate spacer may be prevented.Therefore, the first side etch blocking pattern 160 may prevent thefirst semiconductor filling layer 152 from being etched by the etchant.

A source/drain etch stop layer 185 may extend along the outer sidewall140_OSW of the first gate spacer and a profile of the first source/drainpattern 150. Although not illustrated in the drawings, the source/drainetch stop layer 185 may be disposed on the upper surface of the fieldinsulating layer 105.

The source/drain etch stop layer 185 may include a material having anetch selectivity with respect to a first interlayer insulating layer 190to be described later. The source/drain etch stop layer 185 may include,for example, at least one of silicon nitride (SiN), silicon oxynitride(SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN),silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), andcombinations thereof.

The first interlayer insulating layer 190 may be disposed on thesource/drain etch stop layer 185. The first interlayer insulating layer190 may be disposed on the first source/drain pattern 150. The firstinterlayer insulating layer 190 may not cover the upper surface of thefirst gate capping pattern 145. For example, an upper surface of thefirst interlayer insulating layer 190 may be coplanar with the uppersurface of the first gate capping pattern 145.

The first interlayer insulating layer 190 may include, for example, atleast one of silicon oxide, silicon nitride, silicon oxynitride, and alow-k material. The low-k material may include, for example, fluorinatedtetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ),bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS),octamethyleyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS),trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS),trimethylsilil phosphate (TMSP), polytetrafluoroethylene (PTFE), tonensilazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams suchas polypropylene oxide, carbon doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silicaaerogels, silica xerogels, mesoporous silica, or combinations thereof,but is not limited thereto.

The first source/drain contact 180 is disposed on the first source/drainpattern 150. The first source/drain contact 180 is connected to thefirst source/drain pattern 150. The first source/drain contact 180 maypass through the first interlayer insulating layer 190 and thesource/drain etch stop layer 185 to be connected to the firstsource/drain pattern 150.

A first metal silicide layer 155 may be further disposed between thefirst source/drain contact 180 and the first source/drain pattern 150.

It has been illustrated that the first source/drain contact 180 is asingle layer, but this is only for convenience of explanation, and thepresent disclosure is not limited thereto. The first source/draincontact 180 may include, for example, at least one of a metal, a metalalloy, conductive metal nitride, conductive metal carbide, conductivemetal oxide, conductive metal carbonitride, and a two-dimensional (2D)material.

The first metal silicide layer 155 may include metal silicide.

A second interlayer insulating layer 191 is disposed on the firstinterlayer insulating layer 190. The second interlayer insulating layer191 may include, for example, at least one of silicon oxide, siliconnitride, silicon oxynitride, and a low-k material.

A wiring structure 205 is disposed in the second interlayer insulatinglayer 191. The wiring structure 205 may be connected to the firstsource/drain contact 180. The wiring structure 205 may include a wiringline 207 and a wiring via 206.

It has been illustrated that the wiring line 207 and the wiring via 206are separated from each other, but this is only for convenience ofexplanation, and the present disclosure is not limited thereto. That is,as an example, after the wiring via 206 is formed, the wiring line 207may be formed. As another example, the wiring via 206 and the wiringline 207 may be formed at the same time.

It has been illustrated that each of the wiring line 207 and the wiringvia 206 is a single layer, but this is only for convenience ofexplanation, and the present disclosure is not limited thereto. Each ofthe wiring lines 207 and the wiring vias 206 may include, for example,at least one of a metal, a metal alloy, conductive metal nitride,conductive metal carbide, conductive metal oxide, conductive metalcarbonitride, and a two-dimensional (2D) material.

For example, an upper surface of the first source/drain contact 180 at aportion connected to the wiring structure 205 may be coplanar with anupper surface of the first source/drain contact 180 at a portion that isnot connected to the wiring structure 205.

FIGS. 9 and 10 are views for describing a semiconductor device accordingto some embodiments. FIGS. 11 and 12 are views for describing asemiconductor device according to some embodiments. For convenience ofexplanation, contents different from those described with reference toFIGS. 1 to 8 will be mainly described. For reference, FIGS. 9 and 11 areplan views taken along line C-C of FIG. 2 and viewed from above. FIG. 10is an enlarged view of portion Q of FIG. 9 , and FIG. 12 is an enlargedview of portion Q of FIG. 11 .

Referring to FIGS. 9 and 10 , in a semiconductor device according tosome embodiments, the first side etch blocking pattern 160 may includean etch blocking liner 161 and an etch blocking filling layer 162.

The etch blocking liner 161 extends along the connection sidewall140_CSW of the first gate spacer and the facet surface of the firstsemiconductor liner layer 151. The etch blocking liner 161 extends alongthe facet surface 151_FSW of the inner sidewall 151_ISW of the firstsemiconductor liner layer.

The etch blocking liner 161 includes a first inclined surface 160_SS1 ofthe first side etch blocking pattern and a second inclined surface160_SS2 of the first side etch blocking pattern.

The etch blocking peeling layer 162 is disposed on the etch blockingliner 161. The etch blocking filling layer 162 is disposed between theetch blocking liner 161 and the first semiconductor filling layer 152. Aportion of a connection surface 160_CS of the first side etch blockingpattern is defined by the etch blocking filling layer 162.

The etch blocking liner 161 may include, for example, silicon oxide, butis not limited thereto. The etch blocking filling layer 162 may include,for example, silicon nitride, but is not limited thereto.

Referring to FIGS. 11 and 12 , in the semiconductor device according tosome embodiments, the first source/drain pattern 150 may include a sideair gap 160_AG.

The side air gap 160_AG may be disposed between the first side etchblocking pattern 160 and the first semiconductor filling layer 152. Atleast a portion of the connection surface 160_CS of the first side etchblocking pattern is not in contact with the first semiconductor fillinglayer 152.

Although not illustrated in the drawings, in the plan view at a level ofthe first sheet pattern NS1, the side surface air gap 160_AG may bedisposed between the first side etch blocking pattern 160 and the firstsemiconductor filling layer 152. The side air gap 160_AG may extend inthe third direction D3 between the first side etch blocking pattern 160and the first semiconductor filling layer 152.

It has been illustrated in FIG. 11 that the number of side air gaps160_AG is the same as the number of first side etch blocking patterns160, but the present disclosure is not limited thereto. The number ofside air gaps 160_AG may be smaller than the number of first side etchblocking patterns 160.

FIGS. 13 to 16 are views for describing a semiconductor device accordingto some embodiments. For convenience of explanation, contents differentfrom those described with reference to FIGS. 1 to 8 will be mainlydescribed. For reference, FIG. 14 is a plan view taken along line D-D ofFIG. 13 and viewed from above. FIG. 15 is an enlarged view of a pinningregion 151_PIN of FIG. 13 , and FIG. 16 is an enlarged view of portion Rof FIG. 14 .

Referring to FIGS. 13 to 16 , a semiconductor device according to someembodiments may further include a first internal etch blocking pattern165 disposed in the first source/drain pattern 150.

The first semiconductor liner layer 151 may include pinning regions151_PIN. The first semiconductor liner layer 151 extending along thesidewalls of the first source/drain recess 150R may include the pinningregions 151_PIN. For example, the pinning regions 151_PIN may be formedat positions overlapping the first sheet patterns NS1 in the firstdirection D1.

In the cross-sectional view as illustrated in FIG. 3 , a thickness ofthe first semiconductor liner layer 151 in the pinning region 151_PINmay rapidly decrease. In the pinning region 151_PIN, the thickness ofthe first semiconductor liner layer 151 decreases and then increases asit moves away from the first lower pattern BP1.

In the plan view as illustrated in FIG. 14 , the inner sidewall 151_ISWof the first semiconductor liner layer in the pinning region 151_PIN maybe divided into two portions. For example, in the pinning region151_PIN, the inner sidewall 151_ISW of the first semiconductor linerlayer may meet the outer sidewall 151_OSW of the first semiconductorliner layer. Unlike illustrated in FIG. 14 , in the pinning region151_PIN, the inner sidewall 151_ISW of the first semiconductor linerlayer may be spaced apart from the outer sidewall 151_OSW of the firstsemiconductor liner layer in the first direction D1.

It has been illustrated that one first semiconductor liner layer 151includes one pinning region 151_PIN, but the present disclosure is notlimited thereto. One first semiconductor liner layer 151 may alsoinclude a plurality of pinning regions 151_PIN.

It has been illustrated that some of the first source/drain patterns 150include the pinning regions 151_PIN and the others of the firstsource/drain patterns 150 do not include the pinning regions 151_PIN,but the present disclosure is not limited thereto.

Unlike illustrated in the drawings, the pinning regions 151_PIN may beformed at positions overlapping the inner gate structures INT1_GS1,INT2_GS1, and INT3_GS1 in the first direction D1.

The first internal etch blocking pattern 165 may be disposed in thepinning region 151_PIN. The first internal etch blocking pattern 165 isdisposed between the first semiconductor liner layer 151 and the firstsemiconductor filling layer 152. The first internal etch blockingpattern 165 is in direct contact with the first semiconductor linerlayer 151.

In the plan view, a width of the first internal etch blocking pattern165 in the second direction D2 may increase in the direction away fromthe first gate electrode 120 and the first sheet pattern NS1. The firstinternal etch blocking pattern 165 may have a substantially triangularshape. The first internal etch blocking pattern 165 may include a firstinclined surface 165_SS1, a second inclined surface 165_SS2, and aconnection surface 165_CS. The first inclined surface 165_SS1 of thefirst internal etch blocking pattern and the second inclined surface165_SS2 of the first internal etch blocking pattern are in contact withthe first semiconductor liner layer 151. The connection surface 165_CSof the first internal etch blocking pattern connects the first inclinedsurface 165_SS1 of the first internal etch blocking pattern and thesecond inclined surface 165_SS2 of the first internal etch blockingpattern to each other.

In the cross-sectional view, a width of the first internal etch blockingpattern 165 in the third direction D3 may increase in the direction awayfrom the first gate electrode 120 and the first sheet pattern NS1. Thefirst internal etch blocking pattern 165 may have a triangular shape.The first internal etch blocking pattern 165 may include a thirdinclined surface 165_SS3 and a fourth inclined surface 165_SS4. Thethird inclined surface 165_SS3 of the first internal etch blockingpattern and the fourth inclined surface 165_SS4 of the first internaletch blocking pattern are in contact with the first semiconductor linerlayer 151. The connection surface 165_CS of the first internal etchblocking pattern connects the third inclined surface 165_SS3 of thefirst internal etch blocking pattern and the fourth inclined surface165_SS4 of the first internal etch blocking pattern to each other.

In the semiconductor device according to some embodiments, the entiretyof the connection surface 165_CS of the first internal etch blockingpattern may be in contact with the first semiconductor filling layer152.

The first internal etch blocking pattern 165 includes the same materialas the first side surface etch blocking pattern 160. When the first sideetch blocking pattern 160 has a multilayer structure as illustrated inFIG. 9 , the first internal etch blocking pattern 165 has the samemultilayer structure as the first side etch blocking pattern 160.

FIGS. 17 to 19 are views for describing a semiconductor device accordingto some embodiments. For convenience of explanation, contents differentfrom those described with reference to FIGS. 13 to 16 will mainly bedescribed. For reference, FIG. 17 is a plan view taken along line D-D ofFIG. 13 and viewed from above. FIG. 18 is an enlarged view of a pinningregion 151_PIN of FIG. 13 , and FIG. 19 is an enlarged view of portion Rof FIG. 17 .

Referring to FIGS. 17 to 19 , in a semiconductor device according tosome embodiments, the first source/drain pattern 150 may include aninternal air gap 165_AG.

The internal air gap 165_AG may be disposed between the first internaletch blocking pattern 165 and the first semiconductor filling layer 152.At least a portion of the connection surface 165_CS of the firstinternal etch blocking pattern is not in contact with the firstsemiconductor filling layer 152.

Although not illustrated in the drawings, in a plan view at the level ofthe inner gate structure, the internal air gap 165_AG may be disposedbetween the first internal etch blocking pattern 165 and the firstsemiconductor filling layer 152.

FIGS. 20 and 21 are views for describing a semiconductor deviceaccording to some embodiments. FIGS. 22 and 23 are views for describinga semiconductor device according to some embodiments. For convenience ofexplanation, contents different from those described with reference toFIGS. 1 to 8 will be mainly described. For reference, FIGS. 20 and 22are enlarged views of portion P of FIG. 2 . FIGS. 21 and 23 are planviews taken along line C-C of FIG. 2 and viewed from above.

Referring to FIGS. 2, 20, and 21 , a semiconductor device according tosome embodiments may further include semiconductor residue patterns SP_Rdisposed between the inner gate structures INT1_GS1, INT2_GS1, andINT3_GS1 and the first semiconductor liner layer 151.

In a cross-sectional view as illustrated in FIG. 20 , the semiconductorresidue pattern SP_R may be in contact with the first sheet pattern NS1.The semiconductor residue pattern SP_R may be in contact with the outersidewall 151_OSW of the first semiconductor liner layer and thesidewalls of the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1.

In a plan view as illustrated in FIG. 21 , the semiconductor residuepatterns SP_R may be in contact with the outer sidewall 151_OSW of thefirst semiconductor liner layer, the sidewalls of the inner gatestructures INT1_GS1, INT2_GS1, and INT3_GS1, and the connection sidewall140_CSW of the first gate spacer.

The semiconductor residue pattern SP_R may include, for example,silicon-germanium. A fraction of germanium in the semiconductor residuepattern SP_R is greater than the fraction of germanium in the firstsemiconductor liner layer 151. The semiconductor residue pattern SP_Rmay be a residue remaining after a sacrificial pattern SC_L (see FIG. 48) is removed.

Unlike described above, as an example, the semiconductor residuepatterns SP_R may appear in the cross-sectional view as illustrated inFIG. 20 , but may not appear in the plan view as illustrated FIG. 21 .As another example, the semiconductor residue patterns SP_R may appearin the plan view as illustrated in FIG. 21 , but may not appear in thecross-sectional view as illustrated in FIG. 20 .

Referring to FIGS. 2, 22, and 23 , a semiconductor device according tosome embodiments may further include inner gate air gaps INT_AG disposedbetween the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1 andthe first semiconductor liner layer 151.

In a cross-sectional view as illustrated in FIG. 22 , the inner gate airgaps INT_AG may be disposed between the first semiconductor liner layer151 and the first gate insulating layers 130 of the inner gatestructures INT1_GS1, INT2_GS1, and INT3_GS1. The inner gate air gapsINT_AG may be defined between the first semiconductor liner layer 151,the first sheet patterns NS1, and the inner gate structures INT1_GS1,INT2_GS1, and INT3_GS1.

In a plan view as illustrated in FIG. 23 , the inner gate air gapsINT_AG may be disposed between the first semiconductor liner layer 151,the inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1, and thefirst gate spacer 140.

Unlike described above, as an example, the inner gate air gaps INT_AGmay appear in the cross-sectional view as illustrated in FIG. 22 , butmay not appear in the plan view as illustrated FIG. 23 . As anotherexample, the inner gate air gaps INT_AG may appear in the plan view asillustrated in FIG. 23 , but may not appear in the cross-sectional viewas illustrated in FIG. 22 .

FIG. 24 is a view for describing a semiconductor device according tosome embodiments. FIGS. 25 to 27 are views for describing semiconductordevices according to some embodiments, respectively. For convenience ofexplanation, contents different from those described with reference toFIGS. 1 to 8 will be mainly described. For reference, FIG. 24 is a planview taken along line C-C of FIG. 2 and viewed from above.

Referring to FIG. 24 , in a semiconductor device according to someembodiments, the first side etch blocking pattern 160 may protrudetoward the first gate electrode 120 more than the outer sidewall 151_OSWof the first semiconductor liner layer.

In a process of removing the sacrificial pattern SC_L (see FIG. 48 ), aportion of the first semiconductor liner layer 151 may be removed.Accordingly, the first side etch blocking pattern 160 may protrude morethan the outer sidewall 151_OSW of the first semiconductor liner layer.

Although not illustrated in the drawings, in a plan view at the level ofthe first sheet pattern, the first side etch blocking pattern 160 mayprotrude toward the first sheet pattern NS1 less than the outer sidewall151_OSW of the first semiconductor liner layer.

Referring to FIG. 25 , in a semiconductor device according to someembodiments, the first source/drain recess 150R does not include aplurality of width extension regions 150R_ER (see FIG. 2 ).

The sidewalls of the first source/drain recess 150R do not have a wavyshape (i.e., the sidewalls may be substantially straight or planar).Widths of upper portions of the sidewalls of the first source/drainrecess 150R in the first direction D1 may decrease as it moves away fromthe first lower pattern BP1.

Referring to FIG. 26 , in a semiconductor device according to someembodiments, the upper surface of the first source/drain contact 180 atthe portion that is not connected to the wiring structure 205 is lowerthan the upper surface of the first gate capping pattern 145.

The upper surface of the first source/drain contact 180 at the portionconnected to the wiring structure 205 is lower than the upper surface ofthe first source/drain contact 180 at the portion that is not connectedto the wiring structure 205.

Referring to FIG. 27 , in a semiconductor device according to someembodiments, the first source/drain contact 180 includes a lowersource/drain contact 181 and an upper source/drain contact 182.

The upper source/drain contact 182 may be disposed at a portionconnected to the wiring structure 205. On the other hand, the uppersource/drain contact 182 may not be disposed at a portion that is notconnected to the wiring structure 205.

The wiring line 207 may be connected to the first source/drain contact180 without the wiring via 206 (see FIG. 2 ). The wiring structure 205may not include the wiring via 206 (see FIG. 2 ).

It has been illustrated in FIG. 27 that each of the lower source/draincontact 181 and the upper source/drain contact 182 is a single layer,but this is only for convenience of explanation, and the presentdisclosure is not limited thereto. Each of the lower source/draincontact 181 and the upper source/drain contact 182 may include, forexample, at least one of a metal, a metal alloy, conductive metalnitride, conductive metal carbide, conductive metal oxide, conductivemetal carbonitride, and a two-dimensional (2D) material.

FIGS. 28 to 31 are views for describing a semiconductor device accordingto some embodiments. For reference FIG. 28 is an illustrative plan viewfor describing a semiconductor device according to some embodiments.FIG. 29 is a cross-sectional view taken along line E-E of FIG. 28 . FIG.30 is a plan view taken along line F-F of FIG. 28 and viewed from above.FIG. 31 is a plan view taken along line G-G of FIG. 28 and viewed fromabove.

Meanwhile, a cross-sectional view taken along line A-A of FIG. 28 may bethe same as one of FIGS. 2, 13, and 25 to 27 . In addition, adescription of a first region I of FIG. 28 may be substantially the sameas that described with reference to FIGS. 1 to 27 . Accordingly, in thefollowing description, contents of a second region II of FIG. 28 will bemainly described.

Referring to FIGS. 28 to 31 , a semiconductor device according to someembodiments may include first active patterns AP1, a plurality of firstgate structures GS1, first source/drain patterns 150, first side etchblocking patterns 160 (see FIG. 5 ), second active patterns AP2, aplurality of second gate structures GS2, second source/drain patterns250, and second side etch blocking patterns 260.

A substrate 100 may include a first region I and a second region II. Thefirst region I and the second region II may be regions in which PMOSsare formed.

The first active patterns AP1, the plurality of first gate structuresGS1, the first source/drain patterns 150, and the first side etchblocking patterns 160 are disposed in the first region I of thesubstrate 100. The second active patterns AP2, the plurality of secondgate structures GS2, the second source/drain patterns 250, and thesecond side etch blocking patterns 260 are disposed in the second regionII of the substrate 100.

The second active pattern AP2 may include a second lower pattern BP2 anda plurality of second sheet patterns NS2. The plurality of second sheetpatterns NS2 may be spaced apart from the second lower pattern BP2 inthe third direction D3. The second sheet pattern NS2 includes an uppersurface NS2_US and a lower surface NS2_BS opposite to each other in thethird direction D3. Each of the second lower pattern BP2 and the secondsheet pattern NS2 may include one of silicon or germanium, which is anelemental semiconductor material, a group IV-IV compound semiconductor,or a group III-V compound semiconductor. In the semiconductor deviceaccording to some embodiments, the second lower pattern BP2 may be asilicon lower pattern including silicon, and the second sheet patternNS2 may be a silicon sheet pattern including silicon.

A width W32 of an upper surface BP2_US of the second lower pattern inthe second direction D2 is smaller than a width W31 of the upper surfaceBP1_US of the first lower pattern in the second direction D2. A width ofthe second sheet pattern NS2 in the second direction D2 is smaller thana width of the first sheet pattern NS1 in the second direction D2.

The plurality of second gate structures GS2 may be disposed on thesubstrate 100. The second gate structure GS2 may be disposed on thesecond active pattern AP2. The second gate structure GS2 may cross thesecond active pattern AP2. The second gate structure GS2 may cross thesecond lower pattern BP2. The second gate structure GS2 may surroundeach of the second sheet patterns NS2. The second gate structure GS2 mayinclude a plurality of inner gate structures INT1_GS2, INT2_GS2, andINT3_GS2 disposed between the second sheet patterns NS2 adjacent to eachother in the third direction D3 and between the second lower pattern BP2and the second sheet pattern NS2.

The second gate structure GS2 may include, for example, a second gateelectrode 220, a second gate insulating layer 230, a second gate spacer240, and a second gate capping pattern 245. The second gate spacer 240may include an inner sidewall 240_ISW, a connection sidewall 240_CSW,and an outer sidewall 240_OSW. A description of the second gateelectrode 220, the second gate insulating layer 230, the second gatespacer 240, and the second gate capping pattern 245 is substantially thesame as the description of the first gate electrode 120, the first gateinsulating layer 130, the first gate spacer 140, and the first gatecapping pattern 145, and will thus be omitted below.

The second source/drain pattern 250 may be disposed on the second activepattern AP2. The second source/drain pattern 250 may be disposed on thesecond lower pattern BP2. The second source/drain pattern 250 may beconnected to the second sheet pattern NS2. The second source/drainpattern 250 may be included in a source/drain of a transistor using thesecond sheet pattern NS2 as a channel region.

The second source/drain pattern 250 may be disposed in a secondsource/drain recess 250R. The second source/drain recess 250R mayinclude a plurality of width extension regions 250R_ER. The widthextension region 250R_ER of each of the second source/drain recesses mayinclude a portion where a width thereof in the first direction D1increases and a portion where a width thereof in the first direction D1decreases, as it moves away from the upper surface BP2_US of the secondlower pattern.

The second source/drain pattern 250 may be in contact with the secondsheet pattern NS2 and the second lower pattern BP2. A portion of thesecond source/drain pattern 250 may be in contact with the connectionsidewall 240_CSW of the second gate spacer. The second gate insulatinglayers 230 of the inner gate structures INT1_GS2, INT2_GS2, and INT3_GS2may be in contact with the second source/drain pattern 250.

The second source/drain pattern 250 may include an epitaxial pattern.The second source/drain pattern 250 includes a semiconductor material.The second source/drain pattern 250 may include a second semiconductorliner layer 251 and a second semiconductor filling layer 252. It hasbeen illustrated that the second semiconductor filling layer 252 is asingle layer, but this is only for convenience of explanation, and thepresent disclosure is not limited thereto.

The second semiconductor liner layer 251 may include an outer sidewall251_OSW and an inner sidewall 251_ISW. The inner sidewall 251_ISW of thesecond semiconductor liner layer may include a facet surface 251_FSW anda connection surface 251_CSW. A description of a shape and a material ofthe second source/drain pattern 250 is substantially the same as thedescription of the shape and the material of the first source/drainpattern 150, and will thus be omitted below.

The second side etch blocking pattern 260 may be disposed between thesecond gate spacer 240 and the second source/drain pattern 250. Thesecond side etch blocking pattern 260 may be disposed between the secondgate spacer 240 and the second semiconductor liner layer 251.

In FIGS. 30 and 31 , the second side etch blocking pattern 260 mayextend along the third direction D3 between the second gate spacer 240and the second source/drain pattern 250.

The second side etch blocking pattern 260 may be disposed between theconnection sidewall 240_CSW of the second gate spacer and the facetsurface 251_FSW of the inner sidewall 251_ISW of the secondsemiconductor liner layer. The second side etch blocking pattern 260 maybe disposed between the connection sidewall 240_CSW of the second gatespacer and a facet surface of the second semiconductor liner layer 251.

The second side etch blocking pattern 260 may be in direct contact withthe second gate spacer 240 and the second source/drain pattern 250. Thesecond side etch blocking pattern 260 may be in contact with theconnection sidewall 240_CSW of the second gate spacer and the facetsurface of the second semiconductor liner layer 251.

A width of the second side etch blocking pattern 260 in the seconddirection D2 may increase in the direction away from the second gateelectrode 220. In a plan view, the second side surface etch blockingpattern 260 may have a substantially triangular shape.

In a plan view, the second side etch blocking pattern 260 covers atleast a portion of the facet surface of the second semiconductor linerlayer 251. The second semiconductor filling layer 252 may be in contactwith a portion of the facet surface of the second semiconductor linerlayer 251.

In FIG. 30 , since the second side etch blocking pattern 260 covers aportion of the inner sidewall 251_ISW of the second semiconductor linerlayer 251, a maximum width W41 of the second semiconductor liner layer251 in the second direction D2 is greater than a width W51, in thesecond direction D2, of an interface between the second semiconductorliner layer 251 and the second semiconductor filling layer 252.

In FIG. 31 , a maximum width W42 of the second semiconductor liner layer251 in the second direction D2 is greater than a width W52, in thesecond direction D2, of the interface between the second semiconductorliner layer 251 and the second semiconductor filling layer 252.

In FIG. 30 , a thickness of the second side surface etch blockingpattern 260 in the first direction D1 is a third thickness T21. In FIG.31 , a thickness of the second side surface etch blocking pattern 260 inthe first direction D1 is a fourth thickness T22. It has beenillustrated in FIGS. 30 and 31 that the thickness T21 of the second sidesurface etch blocking pattern 260 at a level of the inner gate structureis greater than the thickness T22 of the second side surface etchblocking pattern 260 at a level of the second sheet pattern, but this isonly for convenience of explanation, and the present disclosure is notlimited thereto.

In FIGS. 5 and 30 , the thickness T11 of the first side etch blockingpattern 160 in the first direction D1 is greater than the thickness T21of the second side etch blocking pattern 260 in the first direction D1.

In FIGS. 6 and 31 , the thickness T21 of the first side etch blockingpattern 160 in the first direction D1 is greater than the thickness T22of the second side etch blocking pattern 260 in the first direction D1.

As an example, the internal etch blocking pattern described withreference to FIGS. 13 to 19 may not be disposed in the secondsource/drain pattern 250.

As another example, the internal etch blocking pattern described withreference to FIGS. 13 to 19 may be disposed in the second source/drainpattern 250. In this case, a thickness, in the first direction D1, ofthe internal etch blocking pattern in the second source/drain pattern250 is smaller than the thickness, in the first direction D1, of thefirst internal etch blocking pattern 165 (see FIG. 14 ) in the firstsource/drain pattern 150.

A second source/drain contact 280 is disposed on the second source/drainpattern 250. The second source/drain contact 280 is connected to thesecond source/drain pattern 250. A second metal silicide layer 255 maybe further disposed between the second source/drain contact 280 and thesecond source/drain pattern 250.

FIG. 32 is a view for describing a semiconductor device according tosome embodiments. For convenience of explanation, contents differentfrom those described with reference to FIGS. 28 to 31 will be mainlydescribed. For reference, FIG. 32 is a plan view taken along line F-F ofFIG. 28 and viewed from above.

Referring to FIG. 32 , in a semiconductor device according to someembodiments, the second side etch blocking pattern 260 (see FIG. 30 ) isnot disposed between the second source/drain pattern 250 and the secondgate spacer 240.

The maximum width W41 of the second semiconductor liner layer 251 in thesecond direction D2 may be the same as the width W51, in the seconddirection D2, of the interface between the second semiconductor linerlayer 251 and the second semiconductor filling layer 252.

Although not illustrated in the drawings, one of ordinary skill in theart to which the present disclosure pertains may perceive a plan viewtaken along line G-G of FIG. 29 and viewed from above through FIG. 32 .

FIGS. 33 to 35 are views for describing a semiconductor device accordingto some embodiments. For reference FIG. 33 is an illustrative plan viewfor describing a semiconductor device according to some embodiments.FIGS. 34 and 35 are cross-sectional views taken along line H-H of FIG.33 .

In addition, a cross-sectional view taken along line A-A of FIG. 33 maybe the same as one of FIGS. 2, 13, and 25 to 27 . In addition, adescription of a first region I of FIG. 33 may be substantially the sameas that described with reference to FIGS. 1 to 27 . Accordingly, in thefollowing description, contents of a third region III of FIG. 33 will bemainly described.

Referring to FIGS. 33 to 35 , a semiconductor device according to someembodiments may include first active patterns AP1, a plurality of firstgate structures GS1, first source/drain patterns 150, first side etchblocking patterns 160 (see FIG. 5 ), third active patterns AP3, aplurality of third gate structures GS3, and third source/drain patterns350.

A substrate 100 may include a first region I and a third region III. Thefirst region I may be a region in which a PMOS is formed, and the thirdregion III may be a region in which an NMOS is formed.

The first active patterns AP1, the plurality of first gate structuresGS1, the first source/drain patterns 150, and the first side etchblocking patterns 160 are disposed in the first region I of thesubstrate 100. The third active patterns AP3, the plurality of thirdgate structures GS3, and the third source/drain patterns 350 aredisposed in the third region III of the substrate 100.

The third active pattern AP3 may include a third lower pattern BP3 and aplurality of third sheet patterns NS3. The plurality of third sheetpatterns NS3 are disposed on an upper surface BP3_US of the third lowerpattern. The third sheet pattern NS3 includes an upper surface NS3_USand a lower surface NS3_BS opposite to each other in the third directionD3. Each of the third lower pattern BP3 and the third sheet pattern NS3may include one of silicon or germanium, which is an elementalsemiconductor material, a group IV-IV compound semiconductor, or a groupIII-V compound semiconductor. In the semiconductor device according tosome embodiments, the third lower pattern BP3 may be a silicon lowerpattern including silicon, and the third sheet pattern NS3 may be asilicon sheet pattern including silicon.

The plurality of third gate structures GS3 may be disposed on thesubstrate 100. The third gate structure GS3 may be disposed on the thirdactive pattern AP3. The third gate structure GS3 may cross the thirdactive pattern AP3. The third gate structure GS3 may cross the thirdlower pattern BP3. The third gate structure GS3 may surround each of thethird sheet patterns NS3. The third gate structure GS3 may include aplurality of inner gate structures INT1_GS3, INT2_GS3, and INT3_GS3disposed between the third sheet patterns NS3 adjacent to each other inthe third direction D3 and between the third lower pattern BP3 and thethird sheet pattern NS3. The third gate structure GS3 may include, forexample, a third gate electrode 320, a third gate insulating layer 330,a third gate spacer 340, and a third gate capping pattern 345.

In FIG. 34 , the third gate spacer 340 is not disposed between theplurality of inner gate structures INT1_GS3, INT2_GS3, and INT3_GS3 andthe third source/drain pattern 350. The third gate insulating layers 330included in the inner gate structures INT1_GS3, INT2_GS3, and INT3_GS3may be in contact with the third source/drain pattern 350.

In FIG. 35 , the third gate structure GS3 may include inner spacersISP1_GS3, ISP2_GS3, and ISP3_GS3. The inner spacers ISP1_GS3, ISP2_GS3,and ISP3_GS3 may be disposed between the third sheet patterns NS3adjacent to each other in the third direction D3 and between the thirdlower pattern BP3 and the third sheet pattern NS3. The inner spacersISP1_GS3, ISP2_GS3, and ISP3_GS3 may be in contact with the third gateinsulating layers 330 included in the inner gate structures INT1_GS3,INT2_GS3, and INT3_GS3. The inner spacers ISP1_GS3, ISP2_GS3, andISP3_GS3 may define a portion of a third source/drain recess 350R.

The third source/drain pattern 350 may be formed on the third activepattern AP3. The third source/drain pattern 350 may be formed on thethird lower pattern BP3. The third source/drain pattern 350 may beconnected to the third sheet pattern NS3. The third source/drain pattern350 may be included in a source/drain of a transistor using the thirdsheet pattern NS3 as a channel region.

The third source/drain pattern 350 may be disposed in the thirdsource/drain recess 350R. A bottom surface of the third source/drainrecess 350R may be defined by the third lower pattern BP3. Sidewalls ofthe third source/drain recess 350R may be defined by the third sheetpatterns NS3 and the third gate structure GS3.

The third source/drain pattern 350 may include an epitaxial pattern. Thethird source/drain pattern 350 may include, for example, silicon orgermanium, which is an elemental semiconductor material. In addition,the third source/drain pattern 350 may include, for example, a binarycompound or a ternary compound including two or more of carbon (C),silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained bydoping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with agroup IV element. For example, the third source/drain pattern 350 mayinclude silicon, silicon-germanium, silicon carbide, or the like, but isnot limited thereto.

The third source/drain pattern 350 may include impurities doped into asemiconductor material. For example, the third source/drain pattern 350may include n-type impurities. The doped impurities may include at leastone of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

In FIG. 34 , the third source/drain recess 350R may include a pluralityof width extension regions 350R_ER.

In FIG. 35 , the third source/drain recess 350R does not include theplurality of width extension regions 350R_ER.

A third source/drain contact 380 is disposed on the third source/drainpattern 350. The third source/drain contact 380 is connected to thethird source/drain pattern 350. A third metal silicide layer 355 may befurther disposed between the third source/drain contact 380 and thethird source/drain pattern 350.

FIGS. 36 to 53 are views for describing intermediate steps of a methodfor fabricating a semiconductor device according to some embodiments.FIGS. 36 to 39, 42, 45, and 50 to 52 may be cross-sectional views takenalong line A-A of FIG. 1 . FIGS. 40 and 41 are plan views taken alongline C-C and line D-D of FIG. 39 and viewed from above, respectively.FIGS. 43 and 44 are plan views taken along line C-C and line D-D of FIG.42 and viewed from above, respectively. FIGS. 46 to 49 are plan viewstaken along line C-C and line D-D of FIG. 45 and viewed from above. FIG.53 is a plan view taken along line C-C of FIG. 52 and viewed from above.

Referring to FIG. 36 , the first lower pattern BP1 and an upper patternstructure U_AP may be formed on the substrate 100.

The first lower pattern BP1 extends in the first direction D1. The upperpattern structure U_AP may be disposed on the first lower pattern BP1.The upper pattern structure U_AP may include sacrificial patterns SC_Land active patterns ACT_L alternately stacked on the first lower patternBP1. For example, the sacrificial pattern SC_L may include asilicon-germanium layer. The active pattern ACT_L may include a siliconlayer. A fraction of germanium in the sacrificial pattern SC_L isgreater than the fraction of germanium in the first semiconductor linerlayer 151 of FIG. 2 .

Next, a dummy gate structure extending in the second direction D2 isformed on the upper pattern structure U_AP. The dummy gate structure mayinclude a dummy gate insulating layer 130 p, a dummy gate electrode 120p, a dummy gate capping layer 120_HM, and a pre-gate spacer 140 p. Thedummy gate insulating layer 130 p may include, for example, siliconoxide, but is not limited thereto. The dummy gate electrode 120 p mayinclude, for example, polysilicon, but is not limited thereto. The dummygate capping layer 120_HM may include, for example, silicon nitride, butis not limited thereto.

The pre-gate spacer 140 p may include an inner sidewall 140_ISW (seeFIG. 40 ), a connection sidewall 140_CSW (see FIG. 40 ), and an outersidewall 140_OSW (see FIG. 40 ).

The inner sidewall 140_ISW of the pre-gate spacer faces a sidewall ofthe dummy gate electrode 120 p extending in the second direction D2. Theouter sidewall 140_OSW of the pre-gate spacer is a surface opposite tothe inner sidewall 140_ISW of the pre-gate spacer. The connectionsidewall 140_CSW of the pre-gate spacer connects the inner sidewall140_ISW2 of the pre-gate spacer and the outer sidewall 140_OSW of thepre-gate spacer to each other.

Referring to FIG. 37 , the first source/drain recesses 150R may beformed in the upper pattern structure U_AP using the dummy gatestructure as a mask.

A portion of the first source/drain recess 150R may be formed in thefirst lower pattern BP1.

Referring to FIG. 38 , portions of the sacrificial patterns SC_L exposedby the first source/drain recesses 150R may be removed.

As a result, width extension regions 150R_ER of a plurality of firstsource/drain recesses may be formed. The first source/drain recess 150Rmay include the width extension regions 150R_ER of the firstsource/drain recess.

In FIGS. 37 and 38 , the first source/drain recess 150R may expose atleast a portion of the connection sidewall 140_CSW (see FIG. 40 ) of thepre-gate spacer.

Referring to FIGS. 39 and 41 , the first semiconductor liner layer 151may be formed along a profile of the first source/drain recess 150R.

The first semiconductor liner layer 151 may include an outer sidewall151_OSW and an inner sidewall 151_ISW. The outer sidewall 151_OSW of thefirst semiconductor liner layer may be in direct contact with thesacrificial patterns SC_L and the active patterns ACT_L. The innersidewall 151_ISW of the second semiconductor liner layer may include afacet surface 151_FSW and a connection surface 151_CSW. The facetsurface 151_FSW of the inner sidewall 151_ISW of the first semiconductorliner layer may extend from the connection sidewall 140_CSW of thepre-gate spacer.

Referring to FIGS. 42 to 44 , a pre-etch blocking layer 160 p is formedon the first semiconductor liner layer 151.

The pre-etch blocking layer 160 p is formed along a profile of the firstsemiconductor liner layer 151. The pre-etch blocking layer 160 p isformed along the inner sidewall 151_ISW of the first semiconductor linerlayer. The pre-etch blocking layer 160 p covers the first semiconductorliner layer 151.

The pre-etch blocking layer 160 p may cover the outer sidewall 140_OSWof the pre-gate spacer and the connection sidewall 140_CSW of thepre-gate spacer.

The pre-etch blocking layer 160 p may be formed using, for example,chemical vapor deposition (CVD), but is not limited thereto.

Referring to FIGS. 45 to 47 , a pre-etch blocking oxide layer 160 p_OXmay be formed on the first semiconductor liner layer 151.

The pre-etch blocking oxide layer 160 p_OX may be formed by oxidizing aportion of the pre-etch blocking layer 160 p. The pre-etch blockinglayer 160 p may include a residue pre-etch blocking layer 160 p_R and apre-etch blocking oxide layer 160 p_OX.

The residue pre-etch blocking layer 160 p_R is disposed between theconnection sidewall 140_CSW of the pre-gate spacer and the facet surface151_FSW of the inner sidewall 151_ISW of the first semiconductor linerlayer. In a plan view, the residue pre-etch blocking layer 160 p_Rcovers at least a portion of the facet surface of the firstsemiconductor liner layer 151.

Referring to FIGS. 48 and 49 , the first side surface etch blockingpattern 160 is formed by removing the pre-etch blocking oxide layer 160p_OX.

The first side etch blocking pattern 160 may be the residue pre-etchblocking layer 160 p_R. The first side etch blocking pattern 160 is incontact with the facet surface of the first semiconductor liner layer151 and the connection sidewall 140_CSW of the pre-gate spacer.

The first side etch blocking pattern 160 may extend in the thirddirection D3.

Referring to FIG. 50 , the first semiconductor filling layer 152 isformed on the first semiconductor liner layer 151.

The first semiconductor filling layer 152 may fill the remainder of thefirst source/drain recess 150R. In FIGS. 5 and 6 , the firstsemiconductor filling layer 152 is formed on the first side etchblocking pattern 160.

Referring to FIG. 51 , the source/drain etch stop layer 185 and thefirst interlayer insulating layer 190 are sequentially formed on thefirst source/drain pattern 150. Next, an upper surface of the dummy gateelectrode 120 p is exposed by removing a portion of the first interlayerinsulating layer 190, a portion of the source/drain etch stop layer 185,and the dummy gate capping layer 120_HM. While the upper surface of thedummy gate electrode 120 p is exposed, the first gate spacer 140 may beformed. For example, the connection sidewall 140_CSW of the pre-gatespacer becomes the connection sidewall of the first gate spacer.

Referring to FIGS. 52 and 53 , the upper pattern structure U_AP betweenthe first gate spacers 140 may be exposed by removing the dummy gateinsulating layer 130 p and the dummy gate electrode 120 p.

Next, the first sheet patterns NS1 may be formed by removing thesacrificial patterns SC_L. As a result, first gate trenches 120 t areformed between the first gate spacers 140. In addition, the first activepattern AP1 including the first lower pattern BP1 and the first sheetpatterns NS1 is formed.

Next, referring to FIG. 2 , the first gate insulating layers 130 and thefirst gate electrodes 120 may be formed in the first gate trenches 120t. In addition, the first gate capping pattern 145 may be formed.

FIGS. 54 and 55 are views for describing semiconductor devices accordingto some embodiments, respectively.

Referring to FIGS. 54 and 55 , a semiconductor device according to someembodiments may include a base material 500, a ruggedness structure500_RS, and a blocking pattern 510.

The base material 500 may include one surface 500_SF. The base material500 may include, for example, at least one of a semiconductor material,an insulating material, and a material including a metal.

The ruggedness structure 500_RS may be a structure recessed from onesurface 500_SF of the base material.

The blocking pattern 510 fills the ruggedness structure 500_RS. Theblocking pattern 510 is in direct contact with a surface of theruggedness structure 500_RS. The blocking pattern 510 is not disposed onone surface 500_SF of the base material.

The blocking pattern 510 may include, for example, at least one of asemiconductor material, an insulating material, and a material includinga metal. In the semiconductor device according to embodiments of thepresent disclosure, the blocking pattern 510 may be made of aninsulating material.

In FIG. 54 , the ruggedness structure 500_RS may be formed in the basematerial made of one material.

In FIG. 55 , the base material 500 may include a first portion 500A anda second portion 500B. The ruggedness structure 500_RS may be formed ina boundary region between the first portion 500A of the base materialand the second portion 500B of the base material.

FIGS. 56 to 59 are views for describing intermediate steps of a methodfor fabricating a semiconductor device according to some embodiments.

Referring to FIG. 56 , the ruggedness structure 500_RS is formed on onesurface 500_SF of the base material.

The ruggedness structure 500_RS may be formed by a deposition process,an etching process or the like, but is not limited thereto.

Referring to FIG. 57 , a pre-blocking layer 510 p is formed on onesurface 500_SF of the base material. The pre-blocking layer 510 p fillsthe ruggedness structure 500_RS.

Referring to FIG. 58 , a pre-blocking oxide layer 510 p_OX is formed onone surface 500_SF of the base material.

The pre-blocking oxide layer 510 p_OX may be formed by oxidizing aportion of the pre-blocking layer 510 p. The pre-blocking layer 510 pmay include a residue pre-blocking layer 510 p_R and the pre-blockingoxide layer 510 p_OX.

Referring to FIG. 59 , the blocking pattern 510 is formed by removingthe pre-blocking oxide layer 510 p_OX. The blocking pattern 510 fillsthe ruggedness structure 500_RS.

The blocking pattern 510 may be the residue pre-blocking layer 510 p_R.

In concluding the detailed description, those skilled in the art willappreciate that many variations and modifications may be made to thepreferred embodiments without substantially departing from theprinciples of the present inventive concept. Therefore, the disclosedpreferred embodiments of the invention are used in a generic anddescriptive sense only and not for purposes of limitation.

1. A semiconductor device comprising: an active pattern comprising alower pattern extending in a first direction and a plurality of sheetpatterns spaced apart from the lower pattern in a second direction; agate structure on the lower pattern and comprising a gate insulatinglayer, a gate electrode, and a gate spacer, the gate electrode extendingin a third direction perpendicular to the first direction; asource/drain pattern on the lower pattern and in contact with the sheetpatterns and the gate insulating layer; and a first etch blockingpattern between the gate spacer and the source/drain pattern, whereinthe gate spacer comprises an inner sidewall facing the gate electrodeand extending in the third direction, and a connection sidewallextending from the inner sidewall of the gate spacer in the firstdirection, the source/drain pattern comprises a semiconductor linerlayer and a semiconductor filling layer on the semiconductor linerlayer, the semiconductor liner layer is in contact with the sheetpatterns, and comprises a facet surface extending from the connectionsidewall of the gate spacer, and the first etch blocking pattern is incontact with the facet surface of the semiconductor liner layer and theconnection sidewall of the gate spacer.
 2. The semiconductor device ofclaim 1, wherein a width of the first etch blocking pattern in the thirddirection increases with distance in the first direction away from thegate electrode.
 3. The semiconductor device of claim 1, wherein thefirst etch blocking pattern comprises an insulating material.
 4. Thesemiconductor device of claim 1, wherein the first etch blocking patterncomprises a blocking liner extending along the facet surface of thesemiconductor liner layer and the connection sidewall of the gatespacer, and a blocking filling layer on the blocking liner.
 5. Thesemiconductor device of claim 1, wherein the gate structure comprises aninner gate structure between the lower pattern and the sheet patternsand between the sheet patterns adjacent to each other, the inner gatestructure comprising the gate electrode and the gate insulating layer,and the first etch blocking pattern is between the inner gate structureand the semiconductor filling layer.
 6. The semiconductor device ofclaim 1, wherein the first etch blocking pattern comprises a firstsurface facing the facet surface of the semiconductor liner layer, asecond surface facing the connection sidewall of the gate spacer, and aconnection surface extending from the first surface to the secondsurface, and an entirety of the connection surface of the first etchblocking pattern is in contact with the semiconductor filling layer. 7.The semiconductor device of claim 1, wherein the source/drain patterncomprises an air gap between the first etch blocking pattern and thesemiconductor filling layer.
 8. The semiconductor device of claim 1,further comprising: a second etch blocking pattern in the source/drainpattern, wherein the second etch blocking pattern is between thesemiconductor liner layer and the semiconductor filling layer, and awidth of the second etch blocking pattern in the third directionincreases with distance in the first direction away from the gateelectrode.
 9. The semiconductor device of claim 8, wherein thesource/drain pattern comprises an air gap between the second etchblocking pattern and the semiconductor filling layer.
 10. Thesemiconductor device of claim 8, wherein the second etch blockingpattern comprises first and second surfaces in contact with thesemiconductor liner layer and a connection surface extending from thefirst surface to the second surface, and an entirety of the connectionsurface of the second etch blocking pattern is in contact with thesemiconductor filling layer.
 11. The semiconductor device of claim 1,wherein each of the semiconductor liner layer and the semiconductorfilling layer comprises silicon-germanium.
 12. A semiconductor devicecomprising: an active pattern comprising a lower pattern extending in afirst direction and a plurality of sheet patterns spaced apart from thelower pattern in a second direction; a gate structure on the lowerpattern and comprising a gate insulating layer, a gate electrode, and agate spacer, the gate electrode extending in a third directionperpendicular to the first direction; and a source/drain pattern on thelower pattern and in contact with the sheet patterns and the gateinsulating layer, wherein the source/drain pattern comprises asemiconductor liner layer and a semiconductor filling layer on thesemiconductor liner layer and in contact with the semiconductor linerlayer, the semiconductor liner layer is in contact with the sheetpatterns, and comprises a facet surface extending from the gate spacer,and in plan view at a level of one of the sheet patterns, a first widthcomprising a maximum width of the semiconductor liner layer in the thirddirection is greater than a second width, in the third direction, of aninterface between the semiconductor liner layer and the semiconductorfilling layer.
 13. The semiconductor device of claim 12, wherein in planview, the semiconductor filling layer is in contact with a portion ofthe facet surface of the semiconductor liner layer.
 14. Thesemiconductor device of claim 12, further comprising: an etch blockingpattern between the gate spacer and the source/drain pattern, whereinthe gate spacer comprises an inner sidewall facing the gate electrodeand extending in the third direction and a connection sidewall extendingfrom the inner sidewall of the gate spacer in the first direction, andthe etch blocking pattern is in contact with the facet surface of thesemiconductor liner layer and the connection sidewall of the gatespacer.
 15. The semiconductor device of claim 14, wherein in plan view,the etch blocking pattern further comprises a third surface extendingbetween the facet surface of the semiconductor liner layer and theconnection sidewall of the gate spacer, and the third surface isconcave..
 16. A semiconductor device comprising: a first active patterncomprising a first lower pattern extending in a first direction and aplurality of first sheet patterns spaced apart from the first lowerpattern in a second direction; a first gate structure on the first lowerpattern and comprising a first gate insulating layer, a first gateelectrode, and a first gate spacer, the first gate electrode extendingin a third direction perpendicular to the first direction; a secondactive pattern comprising a second lower pattern extending in the firstdirection and a plurality of second sheet patterns spaced apart from thesecond lower pattern in the second direction, a width of an uppersurface of the second lower pattern in the third direction being smallerthan a width of an upper surface of the first lower pattern in the thirddirection; a second gate structure on the second lower pattern andcomprising a second gate insulating layer, a second gate electrode, anda second gate spacer, the second gate electrode extending in the thirddirection; a first source/drain pattern on the first lower pattern andin contact with the first sheet patterns and the first gate insulatinglayer; a second source/drain pattern on the second lower pattern and incontact with the second sheet patterns and the second gate insulatinglayer; and a first etch blocking pattern between the first gate spacerand the first source/drain pattern, wherein the first gate spacercomprises an inner sidewall facing the first gate electrode andextending in the third direction and a connection sidewall extendingfrom the inner sidewall of the first gate spacer in the first direction,the first source/drain pattern comprises a semiconductor liner layer anda semiconductor filling layer on the semiconductor liner layer, thesemiconductor liner layer is in contact with the first sheet pattern,and comprises a facet surface extending from the connection sidewall ofthe first gate spacer, and the first etch blocking pattern is in contactwith the facet surface of the semiconductor liner layer and theconnection sidewall of the first gate spacer.
 17. The semiconductordevice of claim 16, wherein the second gate spacer and the secondsource/drain pattern are free of an etch blocking pattern therebetween.18. The semiconductor device of claim 16, further comprising: a secondetch blocking pattern between the second gate spacer and the secondsource/drain pattern, wherein a dimension of the first etch blockingpattern in the first direction is greater than a dimension of the secondetch blocking pattern in the first direction.
 19. The semiconductordevice of claim 16, wherein the first etch blocking pattern comprises ablocking liner extending along the facet surface of the semiconductorliner layer and the connection sidewall of the first gate spacer, and ablocking filling layer on the blocking liner.
 20. The semiconductordevice of claim 16, further comprising: a second etch blocking patternin the first source/drain pattern, wherein the second etch blockingpattern is between the semiconductor liner layer and the semiconductorfilling layer, a width of the second etch blocking pattern in the thirddirection increases with distance from the first gate electrode, and thesecond source/drain pattern is free of an etch blocking pattern therein.21-23. (canceled)